YAMAHA YMZ770C

Pin function description

No. Name I/O Type Function
16 VDD1 — — +5V/+3.3V supply rail (Host CPU supply rail = +5V/+3.3V)
38 VDD2 — — +5V/+3.3V supply rail (external phrase data ROM supply rail = +5V/+3.3V)
55 VDD3 — — +5V/+3.3V supply rail (external phrase data ROM supply rail = +5V/+3.3V)
72 VDD4 — — +5V supply rail
30 VDD5 — — +5V supply rail
17 VSS1 — — Ground
39 VSS2 — — Ground
56 VSS3 — — Ground
73 VSS4 — — Ground
25 AVDD A- — +5V supply rail (analog)
26 AVSS A- — Ground (analog)
21 /RESET I+ CMOS/Schmitt Reset input
36 XI I CMOS Oscillator crystal connection or external clock input
35 XO O — Oscillator crystal connection
34 CLKO O IOL=2mA Clock output connection
19 /SEL I+ CMOS Interface mode select signal
Connect to supply rail (VDD1) or ground (VSS1-4) according to usage *1
15 /CS I CMOS/Schmitt CPU interface chip select signal input
14 /WR I CMOS/Schmitt CPU interface write enable signal input
13 ENA I CMOS/Schmitt CPU interface enable signal input (normal mode 2)
CPU interface write enable signal input (normal more 1)
12 AD I CMOS/Schmitt CPU interface address selection signal input
18 S6M I+ CMOS/Schmitt CPU interface mode select signal
Connect to supply rail (VDD1) or ground (VSS1-4) according to usage *1
4 CD0 I CMOS/Schmitt CPU interface data bus
5 CD1 I CMOS/Schmitt CPU interface data bus
6 CD2 I CMOS/Schmitt CPU interface data bus
7 CD3 I CMOS/Schmitt CPU interface data bus
8 CD4 I CMOS/Schmitt CPU interface data bus
9 CD5 I CMOS/Schmitt CPU interface data bus
10 CD6 I CMOS/Schmitt CPU interface data bus
11 CD7 I CMOS/Schmitt CPU interface data bus
20 MBMD I+ CMOS External phrase data ROM interface data bus width select signal
Connect to supply rail (VDD1) or ground (VSS1-4) according to usage *1
3 MD00 I+ TTL External phrase data ROM interface data bus
2 MD01 I+ TTL External phrase data ROM interface data bus
1 MD02 I+ TTL External phrase data ROM interface data bus
80 MD03 I+ TTL External phrase data ROM interface data bus
79 MD04 I+ TTL External phrase data ROM interface data bus
78 MD05 I+ TTL External phrase data ROM interface data bus
77 MD06 I+ TTL External phrase data ROM interface data bus
76 MD07 I+ TTL External phrase data ROM interface data bus
75 MD08 I+ TTL External phrase data ROM interface data bus
74 MD09 I+ TTL External phrase data ROM interface data bus
71 MD10 I+ TTL External phrase data ROM interface data bus
70 MD11 I+ TTL External phrase data ROM interface data bus
69 MD12 I+ TTL External phrase data ROM interface data bus
68 MD13 I+ TTL External phrase data ROM interface data bus
67 MD14 I+ TTL External phrase data ROM interface data bus
66 MD15 I+ TTL External phrase data ROM interface data bus
65 MA00 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
64 MA01 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
63 MA02 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
62 MA03 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
61 MA04 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
60 MA05 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
59 MA06 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
58 MA07 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
57 MA08 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
54 MA09 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
53 MA10 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
52 MA11 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
51 MA12 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
50 MA13 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
49 MA14 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
48 MA15 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
47 MA16 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
46 MA17 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
45 MA18 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
44 MA19 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
43 MA20 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
42 MA21 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
41 MA22 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
40 MA23 O IOL=2mA/1.6mA *2 External phrase data ROM interface address bus
32 LRO O IOL=2mA Digital output word clock
31 BCO O IOL=2mA Digital output bit clock
33 SDO O IOL=2mA Digital output data
22 /PLAY O IOL=2mA Playback in progress flag
23 AOL AO 0dB=2.5VP-P Analog output L channel
24 AOR AO 0dB=2.5VP-P Analog output R channel
27 VREF AO — Reference voltage pin
28 /TEST0 I+ CMOS LSI test use pin (connect to supply rail (VDD4/VDD5))
29 /TEST1 I+ CMOS LSI test use pin (connect to supply rail (VDD4/VDD5))
37 /TEST2 I CMOS LSI test use pin (connect to supply rail (VDD4/VDD5))

(Notes)

I+:

Input pin with internal pull-up resistor
The pins’ pull-up supply rails are listed below

Input pin with internal pull-up resistor Pull-up supply rail
/RESET pin VDD1
/SEL pin VDD1
S6M pin VDD1
MBMD pin VDD1
MD00-MD15 pins VDD2/VDD3
/TEST0 pin VDD4/VDD5
/TEST1 pin VDD4/VDD5
A:
Analog pin
*1:
If there is a high level of power supply noise, this may affect the input pull-up. If you think this may cause erroneous operation, connect the pin directly to the supply rail or ground.
*2:
When VDD2/VDD3=5V, IOL=2mA. When VDD2/VDD3=3.3V, IOL=1.6mA

Functional description

Supply rails VDD1-VDD5, VSS1-VSS4, AVDD and AVSS

The VDD1-VDD5 pins are digital supply rail pins.

Connect VDD1 pin to a 5V supply rail for 5V host CPU levels, or to a 3.3V supply rail for 3.3V host CPU levels.

Connect VDD2 and VDD3 to a 5V supply rail for 5V external phrase data storage ROM levels, or to a 3.3V supply rail for 3.3V external phrase data storage ROM levels.

Connect the VDD4 and VDD5 to a 5V supply rail irrespective of the host CPU and external phrase data storage ROM levels.

The VSS1-VSS4 pins are digital ground pins. Connect them to the common ground.

The AVDD pin is an analog supply rail pin. Connect it to a 5V supply rail.

The AVSS pin is an analog ground pin.

When the analog supply rail and digital supply rail, and analog ground and digital ground are different rails, it is recommended that the grounds be connected.

Host CPU External phrase data storage ROM VDD1 VDD2/VDD3 VDD4/VDD5 AVDD
5V levels 5V levels 5V 5V 5V 5V
5V levels 3.3V levels 5V 3.3V 5V 5V
3.3V levels 5V levels 3.3V 5V 5V 5V
3.3V levels 3.3V levels 3.3V 3.3V 5V 5V

Concerning the order of pwer supply startup, there is no strict requirement, but it is recommended that all supplies start up within 100ms.

Clock generator XI, XO, CLKO

The XI and XO pins are used for the crystal oscillator circuit configuration.

The oscillator frequencey sets fs (the sampling frequency) proportionally, accoring to the choices listed below.

The CLKO pin is an output clock of either 256fs or 384fs.

The XI pin may also be used as an external clock input. In this configuration, leave the XO pin open.

fs (sampling frequency) XI pin input frequency CLKO output frequency
48kHz/24kHz 18.432MHz 384fs
44.1kHz/22.05kHz 16.9344MHz 384fs
32kHz/16kHz 16.384MHz 256fs

Host CPU interface /SEL, S6M, /CS, /WR, ENA, AD and CD0-CD7

The operation of the /SEL, S6M, /CS, /WR, ENA and AD pins depends on the mode and the current state.

The /SEL pin is an interface mode selection pin.

The S6M pin is a CPU interface mode selection pin.

The CD0-CD7 pins are CPU command data input pins.

Command data writes are controlled by the /CS, /WR, ENA and AD pins.

Connect the /SEL and S6M pins to the supply rail (VDD1) or ground (VSS1-VSS4).

Choose the mode to use from normal mode 1, normal mode 2 and simple access mode.

/SEL S6M /CS /WR ENA AD Function
L * L * * * Simple access mode
H H L L * L Normal mode 1 Address write state
H H L L * H Data write state
H L L L H L Normal mode 2 Address write state
H L L L H H Data write state
H L * * L * Inactive state
H * H * * * Common to normal modes 1 & 2 Inactive state
H * * H * * Inactive state

*: Don’t care

Normal mode 1 (/SEL pin = “H”, S6M pin = “H”)

Place register addresses on the CD0-CD7 pins when the AD pin = “L” and data when the AD pin = “H”.

Register addresses and data are captured inside the LSI on rising edges on the /WR pin.

Normal mode 2 (/SEL pin = “H”, S6M pin = “L”)

Place register addresses on the CD0-CD7 pins when the AD pin = “L” and data when the AD pin = “H”.

Register addresses and data are captured inside the LSI on falling edges on the ENA pin.

Simple access mode (/SEL pin = “L”)

Using the 8-bit data bus (CD0-CD7), sequence control is possible.

External phrase data storage ROM interface MA00-MA23, MD00-MD15 and MBMD

Connect the MBMD pin directly to the supply rail (VDD1) or ground (VSS1-VSS4).

The access time of the external phrase data storage ROM must not exceed 180ns when using 5V levels, or 120ns when using 3.3V levels.

Digital output LRO, BCO and SDO

When the DOEN register = 1, the phrase data is deocded to PCM and output digitally.

16-bit data is output serially MSB first.

fs (the sampling frequency) is set according to the current playback state and the fs setting of the phrase data.

After system reset, before phrase data playback commences, in the initial device state fs (Hz) = XI pin input frequency / 512 and BCO output frequency is set to 64fs.

fs BCO output frequency
48kHz/24kHz 48fs
44.1kHz/22.05kHz 48fs
32kHz/16kHz 64fs

When the DOEN register = 0, the LRO, BCO and SDO pins output “L” level.

When the digital output is unused, leave the LRO, BCO and SDO pins open.

Analog output AOL, AOR, /PLAY and VREF

Phrase data is decoded to PCM, passed through 2 times digital oversampling, a 16-bit DAC and an operational amplifier, and output as an alalog signal on the AOL and AOR pins.

0dB corresponds to an output of 2.5Vpp; the maximum output level is 5.0Vpp.

The /PLAY pin indicates playback status according to the state of the KONx registers ($43h, $47h, $4Bh, $4Fh, $53h, $5Bh, $5Fh), changing from “H” level to “L” level when any channel is playing.

The VREF pin is the analog circuit’s reference voltage output. Connect this to a capacitor if used.

System reset /RESET

When the /RESET pin is at “L” level, the internal registers are initialised. Playback is forcibly stopped.

It is necessary to perform a system reset when the power supply is connected to the LSI.

It is necessary to hold the /RESET pin at “L” level until all power supply rails have started up and reached regulated levels.

After the system reset is released (“L”→“H”), it takes 262144 clock periods of the XI pin clock input for the internal registers to be initialised, during which period commands from the host CPU will be disregarded.

Hold the /RESET pin at “L” level before the supply rails start up.

Phrase playback control register map

The LSI’s playback is controlled by the following registers.

ADRS Playback channel D7 D6 D5 D4 D3 D2 D1 D0
$00h ALL DOEN MUTE
$01h VLMA (overall AMM volume)
$02h CPL (clip limiter) BSL (boost level)
$40h Channel 0 MSN0 (phrase number selection)
$41h VLM0 (volume)
$42h PAN0 (pan)
$43h KON0 LOOP0
$44h Channel 1 MSN1 (phrase number selection)
$45h VLM1 (volume)
$46h PAN1 (pan)
$47h KON1 LOOP1
$48h Channel 2 MSN2 (phrase number selection)
$49h VLM2 (volume)
$4Ah PAN2 (pan)
$4Bh KON2 LOOP2
$4Ch Channel 3 MSN3 (phrase number selection)
$4Dh VLM3 (volume)
$4Eh PAN3 (pan)
$4Fh KON3 LOOP3
$50h Channel 4 MSN4 (phrase number selection)
$51h VLM4 (volume)
$52h PAN4 (pan)
$53h KON4 LOOP4
$54h Channel 5 MSN5 (phrase number selection)
$55h VLM5 (volume)
$56h PAN5 (pan)
$57h KON5 LOOP5
$58h Channel 6 MSN6 (phrase number selection)
$59h VLM6 (volume)
$5Ah PAN6 (pan)
$5Bh KON6 LOOP6
$5Ch Channel 7 MSN7 (phrase number selection)
$5Dh VLM7 (volume)
$5Eh PAN7 (pan)
$5Fh KON7 LOOP7

Note:          Write “0” to these locations.

Sequencer control register map

The LSI’s 8 internal sequencer systems are controlled by the following registers.

ADRS Sequencer D7 D6 D5 D4 D3 D2 D1 D0
$80h Sequencer 0 SQSN0 (sequence code selection)
$81h SQON0 SQLP0
$82h TMRH0 (wait timer H byte)
$83h TMRL0 (wait timer L byte)
$84h TGST0 (ON trigger playback channel selection)
$85h TGEN0 (OFF trigger playback channel selection)
$86h SQOF0 (sequencer end time playback stop channel selection)
$88h “01h”
$90h Sequencer 1 SQSN1 (sequence code selection)
$91h SQON1 SQLP1
$92h TMRH1 (wait timer H byte)
$93h TMRL1 (wait timer L byte)
$94h TGST1 (ON trigger playback channel selection)
$95h TGEN1 (OFF trigger playback channel selection)
$96h SQOF1 (sequencer end time playback stop channel selection)
$98h “01h”
$A0h Sequencer 2 SQSN2 (sequence code selection)
$A1h SQON2 SQLP2
$A2h TMRH2 (wait timer H byte)
$A3h TMRL2 (wait timer L byte)
$A4h TGST2 (ON trigger playback channel selection)
$A5h TGEN2 (OFF trigger playback channel selection)
$A6h SQOF2 (sequencer end time playback stop channel selection)
$A8h “01h”
$B0h Sequencer 3 SQSN3 (sequence code selection)
$B1h SQON3 SQLP3
$B2h TMRH3 (wait timer H byte)
$B3h TMRL3 (wait timer L byte)
$B4h TGST3 (ON trigger playback channel selection)
$B5h TGEN3 (OFF trigger playback channel selection)
$B6h SQOF3 (sequencer end time playback stop channel selection)
$B8h “01h”
$C0h Sequencer 4 SQSN4 (sequence code selection)
$C1h SQON4 SQLP4
$C2h TMRH4 (wait timer H byte)
$C3h TMRL4 (wait timer L byte)
$C4h TGST4 (ON trigger playback channel selection)
$C5h TGEN4 (OFF trigger playback channel selection)
$C6h SQOF4 (sequencer end time playback stop channel selection)
$C8h “01h”
$D0h Sequencer 5 SQSN5 (sequence code selection)
$D1h SQON5 SQLP5
$D2h TMRH5 (wait timer H byte)
$D3h TMRL5 (wait timer L byte)
$D4h TGST5 (ON trigger playback channel selection)
$D5h TGEN5 (OFF trigger playback channel selection)
$D6h SQOF5 (sequencer end time playback stop channel selection)
$D8h “01h”
$E0h Sequencer 6 SQSN6 (sequence code selection)
$E1h SQON6 SQLP6
$E2h TMRH6 (wait timer H byte)
$E3h TMRL6 (wait timer L byte)
$E4h TGST6 (ON trigger playback channel selection)
$E5h TGEN6 (OFF trigger playback channel selection)
$E6h SQOF6 (sequencer end time playback stop channel selection)
$E8h “01h”
$F0h Sequencer 7 SQSN7 (sequence code selection)
$F1h SQON7 SQLP7
$F2h TMRH7 (wait timer H byte)
$F3h TMRL7 (wait timer L byte)
$F4h TGST7 (ON trigger playback channel selection)
$F5h TGEN7 (OFF trigger playback channel selection)
$F6h SQOF7 (sequencer end time playback stop channel selection)
$F8h “01h”

Notes:
         Write “0” to these locations.
Set $88h, $98h, $A8h, $B8h, $C8h, $D8h, $E8h and $F8h to “01h”.

External phrase data storage ROM address map

For either an 8-bit data bus or a 16-bit data bus, the LSI calculates 1 address = 8 data bits. In the case when an 8-bit data bus external phrase data storage ROM is connected, address = ROM address. In the case when a 16-bit data bus external phrase data storage ROM is connected, addresses are assigned to an “H” byte and an “L” byte in sequence.

ADRS — D7 D6 D5 D4 D3 D2 D1 D0
$000_0000h Phrase number 0 ATBL00
$000_0001h MST00 (phrase data start address bits 24-0, MSB first)
$000_0002h
$000_0003h
$000_0004h Phrase number 1 ATBL01
$000_0005h MST01 (phrase data start address bits 24-0, MSB first)
$000_0006h
$000_0007h
… … …
$000_03FCh Phrase number 255 ATBLFF
$000_03FDh MSTFF (phrase data start address bits 24-0, MSB first)
$000_03FEh
$000_03FFh
$000_0400h Sequence code 0
$000_0401h SQCD00 (sequence code data start address bits 24-0, MSB first)
$000_0402h
$000_0403h
$000_0404h Sequence code 1
$000_0405h SQCD01 (sequence code data start address bits 24-0, MSB first)
$000_0406h
$000_0407h
… … …
$000_07FCh Sequence code 255
$000_07FDh SQCDFF (sequence code data start address bits 24-0, MSB first)
$000_07FEh
$000_07FFh
$000_0800h Simple access code 0
$000_0801h SACD00 (simple access code data start address bits 24-0, MSB first)
$000_0802h
$000_0803h
$000_0804h Simple access code 1
$000_0805h SACD01 (simple access code data start address bits 24-0, MSB first)
$000_0806h
$000_0807h
… … …
$000_0BFCh Simple access code 255
$000_0BFDh SACDFF (simple access code data start address bits 24-0, MSB first)
$000_0BFEh
$000_0BFFh

Note:          Set these locations to “0”.